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2.5 v to 5.5 v, parallel interface octal voltage output 8-/10-/12-bit dacs ad5346/ad5347/ad5348 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. features ad5346: octal 8-bit dac ad5347: octal 10-bit dac ad5348: octal 12-bit dac low power operation: 1.4 ma (max) @ 3.6 v power-down to 120 na @ 3 v, 400 na @ 5 v guaranteed monotonic by design over all codes rail-to-rail output range: 0 v to v ref or 0 v to 2 v ref power-on reset to 0 v simultaneous update of dac outputs via ldac pin asynchronous clr facility readback buffered/unbuffered reference inputs 20 ns wr time 38-lead tssop/6 mm 6 mm 40-lead lfcsp packaging temperature range: C40c to +105c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources optical networking automatic test equipment mobile communications programmable attenuators industrial process control general description the ad5346/ad5347/ad5348 1 are octal 8-, 10-, and 12-bit dacs, operating from a 2.5 v to 5.5 v supply. these devices incorporate an on-chip output buffer that can drive the output to both supply rails, and also allow a choice of buffered or unbuffered reference input. the ad5346/ad5347/ad5348 have a parallel interface. cs selects the device and data is loaded into the input registers on the rising edge of wr . a readback feature allows the internal dac registers to be read back through the digital port. the gain pin on these devices allows the output range to be set at 0 v to v ref or 0 v to 2 v ref . input data to the dacs is double-buffered, allowing simultane- ous update of multiple dacs in a system using the ldac pin. an asynchronous clr input is also provided, which resets the contents of the input register and the dac register to all zeros. these devices also incorporate a power-on reset circuit that ensures that the dac output powers on to 0 v and remains there until valid data is written to the device. all three parts are pin compatible, which allows users to select the amount of resolution appropriate for their application without redesigning their circuit board. functional block diagram input register dac register string dac c string dac a string dac b string dac d string dac e string dac f string dac g string dac h dgnd v out b v out c v out d v out e v out g v out h v out f v dd power-on reset v out a v ref ef v ref ab pd inter- face logic gain db11 db0 cs wr a0 a1 clr ldac . . . buf a2 rd v ref gh v ref cd agnd buffer buffer buffer buffer buffer buffer buffer buffer input register input register input register input register input register input register input register dac register dac register dac register dac register dac register dac register dac register ad5348 power-down logic 03331-0-001 figure 1. 1 protected by u.s. patent no. 5,969,657.
ad5346/ad5347/ad5348 rev. 0 | page 2 of 24 table of contents specifications ..................................................................................... 3 ac characteristics ............................................................................ 4 timing characteristics ..................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 ad5346 pin configurations and function descriptions ........... 7 ad5347 pin configurations and function descriptions ........... 8 ad5348 pin configurations and function descriptions ........... 9 te r m i no l o g y .................................................................................... 10 typical performance characteristics ........................................... 12 functional description .................................................................. 16 digital-to-analog section ......................................................... 16 resistor string ............................................................................. 16 dac reference input ................................................................. 16 output amplifier ........................................................................ 16 parallel interface ......................................................................... 17 power-on reset .......................................................................... 17 power-down mode .................................................................... 17 suggested data bus formats ..................................................... 18 applications information .............................................................. 19 typical application circuits ..................................................... 19 driving v dd from the reference voltage ................................. 19 bipolar operation using the ad5346/ad5347/ad5348 ..... 19 decoding multiple ad5346/ad5347/ad5348s .................... 20 ad5346/ad5347/ad5348 as digitally programmable window detectors ...................................................................... 20 programmable current source ................................................ 20 coarse and fine adjustment using the ad5346/ad5347/ad5348 ....................................................... 21 power supply bypassing and grounding ................................ 21 outline dimensions ....................................................................... 23 ordering guides ......................................................................... 24 revision history revision 0: initial version
ad5346/ad5347/ad5348 rev. 0 | page 3 of 24 specifications table 1. v dd = 2.5 v to 5.5 v; v ref = 2 v; r l = 2 k? to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted b version 1 parameter 2 min typ max unit conditions/comments dc performance 3 , 4 ad5346 resolution 8 bits relative accuracy 0.15 1 lsb differential nonlinearity 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5347 resolution 10 bits relative accuracy 0.5 4 lsb differential nonlinearity 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5348 resolution 12 bits relative accuracy 2 16 lsb differential nonlinearity 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 % of fsr gain error 0.1 1 % of fsr lower deadband 5 10 60 mv lower deadband exis ts only if offset error is neg ative upper deadband 5 10 60 mv v dd = 5 v; upper deadband exists only if v ref = v dd offset error drift 6 C12 ppm of fsr/c gain error drift 6 C5 ppm of fsr/c dc power supply rejection ratio 6 C60 db ?v dd = 10% dc crosstalk 6 200 v r l = 2 k? to gnd, 2 k? to v dd ; c l = 200 pf to gnd; gain = +1 dac reference input 6 v ref input range 1 v dd v buffered reference mode v ref input range 0.25 v dd v unbuffered reference mode v ref input impedance >10 m? buffere d reference mode and power-down mod e 90 k? gain = +1; input impedance = r dac 45 k? gain = +2; input impedance = r dac reference feedthrough C90 db frequency = 10 khz channel-to-channel isolation C75 db frequency = 10 khz output characteristics 6 minimum output voltage 4, 7 0.001 v min rail-to-rail operation maximum output voltage 4, 7 v dd C 0.001 v max dc output impedance 0.5 ? short circuit current 25 ma v dd = 5 v 16 ma v dd = 3 v power-up time 2.5 s coming out of power-down mode; v dd = 5 v 5 s coming out of power-down mode; v dd = 3 v logic inputs 6 input current 1 a v il , input low voltage 0.8 v v dd = 5 v 10% 0.7 v v dd = 3 v 10% 0.6 v v dd = 2.5 v v ih , input high voltage 1.7 v v dd = 2.5 v to 5.5 v pin capacitance 5 pf
ad5346/ad5347/ad5348 rev. 0 | page 4 of 24 b version 1 parameter 2 min typ max unit conditions/comments logic outputs 6 v dd = 4.5 v to 5.5 v output low voltage, v ol 0.4 v i sink = 200 a output high voltage, v oh v dd C 1 v i source = 200 a v dd = 2.5 v to 3.6 v output low voltage, v ol 0.4 v i sink = 200 a output high voltage, v oh v dd C 0.5 v i source = 200 a power requirements v dd 2.5 5.5 v i dd (normal mode) v ih = v dd , v il = gnd v dd = 4.5 v to 5.5 v 1 1.65 ma all da cs in unbuffered mode. in buffered mode, v dd = 2.5 v to 3.6 v 0.8 1.4 ma extra current is typically x a per dac, where x = 5 a + v ref /r dac i dd (power-down mode) v ih = v dd , v il = gnd v dd = 4.5 v to 5.5 v 0.4 1 a v dd = 2.5 v to 3.6 v 0.12 1 a see footnotes after the ac characteristics table. ac characteristics 6 table 2. v dd = 2.5 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted b version 1 parameter 2 min typ max unit conditions/comments output voltage settling time v ref = 2 v ad5346 6 8 s 1/4 scale to 3/4 scale change (40 h to c0 h) ad5347 7 9 s 1/4 scale to 3/ 4 scale change (100 h to 300 h) ad5348 8 10 s 1/4 scale to 3/4 scale change (400 h to c00 h) slew rate 0.7 v/s major code transition glitch energy 8 nv-s 1 lsb change around major carry digital feedthrough 0.5 nv-s digital crosstalk 1 nv-s analog crosstalk 1 nv-s dac-to-dac crosstalk 3.5 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p; unbuffered mode total harmonic distortion C70 db v ref = 2. v 0.1 v p-p; frequenc y = 10 khz; unbuffered mode 1 temperature range: b versio n: C40c to +105c; typical specifications are at 25c. 2 see terminology section. 3 linearity is tested using a reduced code range: ad5346 (code 8 to 255); ad5347 (c ode 28 to 1023); ad5348 (code 115 to 4095). 4 dc specifications tested with outputs unloaded. 5 this corresponds to x codes. x = deadband voltage/lsb size. 6 guaranteed by design and characterization, not production tested. 7 for the amplifier output to reach its minimum voltage, offset error must be negative. for the amplifier output to reach its ma ximum voltage, v ref = v dd and the offset plus gain error must be positive. i oh i ol to output pin v oh (min) + v ol (max) 2 c l 50pf 200 a 200 a 03331-0-002 figure 2. load circuit for digital output timing specifications
ad5346/ad5347/ad5348 rev. 0 | page 5 of 24 timing characteristics 1, 2, 3 table 3. v dd = 2.5 v to 5.5 v; all specifications t min to t max , unless otherwise noted parameter limit at t min , t max unit condition/comments data write mode (figure 3) t 1 0 ns min cs to wr setup time t 2 0 ns min cs to wr hold time t 3 20 ns min wr pulse width t 4 5 ns min data, gain, buf setup time t 5 4.5 ns min data, gain, buf hold time t 6 5 ns min synchronous mode. wr falling to ldac falling. t 7 5 ns min synchronous mode. ldac falling to wr rising. t 8 4.5 ns min synchronous mode. wr rising to ldac rising. t 9 5 ns min asynchronous mode. ldac rising to wr rising. t 10 4.5 ns min asynchronous mode. wr rising to ldac falling. t 11 20 ns min ldac pulse width t 12 10 ns min clr pulse width t 13 20 ns min time between wr cycles t 14 20 ns min a0, a1, a2 setup time t 15 0 ns min a0, a1, a2 hold time data readback mode (figure 4) t 16 0 ns min a0, a1, a2 to cs setup time t 17 0 ns min a0, a1, a2 to cs hold time t 18 0 ns min cs to falling edge of rd t 19 20 ns min rd pulse width; v dd = 3.6 v to 5.5 v 30 ns min rd pulse width; v dd = 2.5 v to 3.6 v t 20 0 ns min cs to rd hold time t 21 22 ns max data access time after falling edge of rd ; v dd = 3.6 v to 5.5 v 30 ns max data access time after falling edge of rd v dd = 2.5 v to 3.6 v t 22 4 ns min bus relinquish time after rising edge of rd 30 ns max t 23 22 ns max cs falling edge to data; v dd = 3.6 v to 5.5 v 30 ns max cs falling edge to data; v dd = 2.5 v to 3.6 v t 24 30 ns min time between rd cycles t 25 30 ns min time from rd to wr t 26 30 ns min time from wr to rd , v dd = 3.6 v to 5.5 v 50 ns min time from wr to rd , v dd = 2.5 v to 3.6 v 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 see figure 2. cs wr data, gain, buf ldac 1 ldac 2 clr notes 1. synchronous ldac update mode 2. asynchronous ldac update mode a0?a2 t 1 t 2 t 3 t 4 t 7 t 9 t 10 t 11 t 12 t 5 t 15 t 8 t 14 t 6 t 13 03331-0-003 cs a0?a2 rd wr data t 16 t 18 t 25 t 20 t 22 t 21 t 17 t 26 t 24 t 19 t 23 03331-0-004 figure 3. parallel interface write timing diagram figure 4. parallel interface read timing diagram
ad5346/ad5347/ad5348 rev. 0 | page 6 of 24 absolute maximum ratings table 4. t a = 25c, unless otherwise noted parameter rating v dd to gnd C0.3 v to +7 v digital input voltage to gnd C0.3 v to v dd + 0.3 v digital output voltage to gnd C0.3 v to v dd + 0.3 v reference input voltage to gnd C0.3 v to v dd + 0.3 v v out to gnd C0.3 v to v dd + 0.3 v operating temperature range industrial (b version) C40c to +105c storage temperature range C65c to +150c junction temperature 150c 38-lead tssop package power dissipation (t j max ? t a )/ ja mw ja thermal impedance 98.3c/w jc thermal impedance 8.9c/w 40-lead lfcsp package power dissipation (t j max ? t a )/ ja mw ja thermal impedance (3-layer board) 29.6c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5346/ad5347/ad5348 rev. 0 | page 7 of 24 ad5346 pin configurations and function descriptions top view (not to scale) 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ad5346 ldac a1 a0 wr cs agnd v out d v ref cd v ref ef v ref gh v out c v out b v out a v ref ab pd v dd db 0 db 1 db 2 clr gain db 7 db 6 db 3 db 4 db 5 8-bit v out h v out g v out f v out e dgnd a2 rd buf dgnd dgnd dgnd dgnd 03331-0-005 figure 5. ad5346 pin configurationtssop 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 ldac a1 a0 wr cs agnd v out d v ref cd v ref ef v ref gh v out c v out b v out a v ref ab pd v dd db 0 db 1 db 2 clr gain db 7 db 6 db 3 db 4 db 5 v out h v out g v out f v out e dgnd a2 rd buf agnd v dd top view (not to scale) ad5346 8-bit dgnd dgnd dgnd dgnd 03331-0-006 figure 6. ad5346 pin configurationlfcsp table 5. ad5346 pin function descriptions pin number tssop lfcsp mnemonic function 1 35 v ref gh reference input for dacs g and h. 2 36 v ref ef reference input for dacs e and f. 3 37 v ref cd reference input for dacs c and d. 4 38, 39 v dd power supply pin(s). this part can operate from 2. 5 v to 5.5 v, and the su pply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. both v dd pins on the lfcsp package must be at the same potential. 5 40 v ref ab reference input for dacs a and b. 6C9, 11C14 1C4, 7C10 v out x output of dac x. buffered outp ut with rail-to-rail operation. 10 5, 6 agnd analog ground. ground reference for analog circuitry. 15, 21C24 11, 17C20 dgnd digital ground. ground reference for digital circuitry. 16 12 buf buffer control pin. controls whether the re ference input to the dac is buffered or unbuffered. 17 13 ldac active low control input. updates the dac registers with the contents of the input registers, which allows all dac outputs to be simultaneously updated. 18 14 a0 lsb address pin. selects which dac is to be written to. 19 15 a1 address pin. selects which dac is to be written to. 20 16 a2 msb address pin. selects which dac is to be written to. 25C32 21C28 db 0 Cdb 7 eight parallel data inputs. db 7 is the msb of these eight bits. 33 29 cs active low chip select input. used in conjunction with wr to write data to the parallel interface, or with rd to read back data from a dac. 34 30 rd active low read input. used in conjunction with cs to read data back from the internal dacs. 35 31 wr active low write input. used in conjunction with cs to write data to the parallel interface. 36 32 gain gain control pin. controls whet her the output range from the dac is 0 v to v ref or 0 v to 2 v ref. 37 33 clr asynchronous active low control in put. clears all input registers and dac registers to zeros. 38 34 pd power-down pin. this active low control pin puts all dacs into power-down mode.
ad5346/ad5347/ad5348 rev. 0 | page 8 of 24 ad5347 pin configurations and function descriptions top view (not to scale) 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ad5347 ldac a1 a0 wr cs agnd v out d v ref cd v ref ef v ref gh v out c v out b v out a v ref ab pd v dd db 2 db 3 db 4 clr gain db 9 db 8 db 5 db 6 db 7 10-bit v out h v out g v out f v out e dgnd a2 rd buf db 0 dgnd db 1 dgnd 03331-0-007 figure 7. ad5347 pin configurationtssop 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 ldac a1 a0 wr cs agnd v out d v ref cd v ref ef v ref gh v out c v out b v out a v ref ab pd v dd db 2 db 3 db 4 clr gain db 9 db 8 db 5 db 6 db 7 v out h v out g v out f v out e dgnd a2 rd buf agnd v dd top view (not to scale) ad5347 10-bit db 1 db 0 dgnd dgnd 03331-0-008 figure 8. ad5347 pin configurationlfcsp table 6. ad5347 pin function descriptions pin number tssop lfcsp mnemonic function 1 35 v ref gh reference input for dacs g and h. 2 36 v ref ef reference input for dacs e and f. 3 37 v ref cd reference input for dacs c and d. 4 38, 39 v dd power supply pin(s). this part can operate from 2. 5 v to 5.5 v, and the su pply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. both v dd pins on the lfcsp package must be at the same potential. 5 40 v ref ab reference input for dacs a and b. 6C9, 11C14 1C4, 7C10 v out x output of dac x. buffered outp ut with rail-to-rail operation. 10 5, 6 agnd analog ground. ground reference for analog circuitry. 15, 21C22 11, 17C18 dgnd digital ground. ground reference for digital circuitry. 16 12 buf buffer control pin. controls whether the refe rence input to the dac is buffered or unbuffered. 17 13 ldac active low control input. updates the dac registers with the contents of the input registers, which allows all dac outputs to be simultaneously updated. 18 14 a0 lsb address pin. selects which dac is to be written to. 19 15 a1 address pin. selects which dac is to be written to. 20 16 a2 msb address pin. selects which dac is to be written to. 23C32 19C28 db 0 Cdb 9 ten parallel data inputs. db 9 is the msb of these ten bits. 33 29 cs active low chip select input. used in conjunction with wr to write data to the parallel interface, or with rd to read back data from a dac. 34 30 rd active low read input. used in conjunction with cs to read data back from the internal dacs. 35 31 wr active low write input. used in conjunction with cs to write data to the parallel interface. 36 32 gain gain control pin. controls whether the output range from the dac is 0 v to v ref or 0 v to 2 v ref . 37 33 clr asynchronous active low control in put. clears all input registers and dac registers to zeros. 38 34 pd power-down pin. this active low control pin puts all dacs into power-down mode.
ad5346/ad5347/ad5348 rev. 0 | page 9 of 24 ad5348 pin configurations and function descriptions top view (not to scale) 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ad5348 ldac a1 a0 wr cs agnd v out d v ref cd v ref ef v ref gh v out c v out b v out a v ref ab pd v dd db 4 db 5 db 6 clr gain db 11 db 10 db 7 db 8 db 9 12-bit v out h v out g v out f v out e dgnd a2 rd buf db 2 db 0 db 3 db 1 03331-0-009 figure 9. ad5348 pin configurationtssop 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 ldac a1 a0 wr cs agnd v out d v ref cd v ref ef v ref gh v out c v out b v out a v ref ab pd v dd db 4 db 5 db 6 clr gain db 11 db 10 db 7 db 8 db 9 v out h v out g v out f v out e dgnd a2 rd buf agnd v dd top view (not to scale) ad5348 12-bit db 3 db 2 db 1 db 0 03331-0-010 figure 10. ad5348 pin configurationlfcsp table 7. ad5348 pin function descriptions pin number tssop lfcsp mnemonic function 1 35 v ref gh reference input for dacs g and h. 2 36 v ref ef reference input for dacs e and f. 3 37 v ref cd reference input for dacs c and d. 4 38, 39 v dd power supply pin(s). this part can operate from 2.5 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. both v dd pins on the lfcsp package must be at the same potential. 5 40 v ref ab reference input for dacs a and b. 6C9, 11C14 1C4, 7C10 v out x output of dac x. buffered outp ut with rail-to-rail operation. 10 5, 6 agnd analog ground. ground reference for analog circuitry. 15 11 dgnd digital ground. ground reference for digital circuitry. 16 12 buf buffer control pin. controls whether the re ference input to the dac is buffered or unbuffered. 17 13 ldac active low control input. updates the dac registers with the contents of the input registers, which allows all dac outputs to be simultaneously updated. 18 14 a0 lsb address pin. selects which dac is to be written to. 19 15 a1 address pin. selects which dac is to be written to. 20 16 a2 msb address pin. selects which dac is to be written to. 21C32 17C28 db 0 Cdb 11 twelve parallel data inputs. db 11 is the msb of these 12 bits. 33 29 cs active low chip select input. used in conjunction with wr to write data to the parallel interface, or with rd to read back data from a dac. 34 30 rd active low read input. used in conjunction with cs to read data back from the internal dacs. 35 31 wr active low write input. used in conjunction with cs to write data to the parallel interface. 36 32 gain gain control pin. controls whet her the output range from the dac is 0 v to v ref or 0 v to 2 v ref . 37 33 clr asynchronous active low control in put. clears all input registers and dac registers to zeros. 38 34 pd power-down pin. this active low control pin puts all dacs into power-down mode.
ad5346/ad5347/ad5348 rev. 0 | page 10 of 24 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the actual endpoints of the dac transfer function. typical inl versus code plots can be seen in figure 14, figure 15, and figure 16. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. typical dnl versus code plots can be seen in figure 17, figure 18, and figure 19. gain error this is a measure of the span error of the dac, including any error in the gain of the buffer amplifier. it is the deviation in slope of the actual dac transfer characteristic from the ideal and is expressed as a percentage of the full-scale range. this is illustrated in figure 11. offset error this is a measure of the offset error of the dac and the output amplifier. it is expressed as a percentage of the full-scale range. if the offset voltage is positive, the output voltage still positive at zero input code. this is shown in figure 12. because the dacs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. instead, there is a code close to zero at which the amplifier output saturates (amplifier footroom). below this code there is a dead band over which the output voltage does not change. this is illustrated in figure 13. output v oltage dac code positive gain error negative gain error actual ideal 03331-0-011 figure 11. gain error output voltage dac code positive offset gain error and offset error actual ideal 03331-0-012 figure 12. positive offset error and gain error amplifier footroom (~1mv) negative offset output voltage dac code gain error and offset error deadband codes actual ideal negative offset 03331-0-013 figure 13. negative offset error and gain error
ad5346/ad5347/ad5348 rev. 0 | page 11 of 24 offset error drift this is a measure of the change in offset error with changes in t emperature. it is expressed in (ppm of full-scale range)/c. gain error drift this is a measure of the change in gain error with changes in t emperature. it is expressed in (ppm of full-scale range)/c. dc power-supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in t he supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in db. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac at midscale in r esponse to a full-scale code change (all 0s to all 1s and vice versa) and output change of another dac. it is expressed in v. reference feedthrough this is the ratio of the amplitude of the signal at the dac o utput to the reference input when the dac output is not being updated, i.e., ldac is high. it is expressed in db. channel-to-channel isolation this is a ratio of the amplitude of the signal at the output of one d ac to a sine wave on the reference inputs of the other dacs. it is measured by grounding one v ref pin and applying a 10 khz, 4 v p-p sine wave to the other v ref pins. it is expressed in db. major-code transition glitch energy this is the energy of the impulse injected into the analog output w hen the dac changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough this is a measure of the impulse injected into the analog output o f the dac from the digital input pins of the device, but it is measured when the dac is not being written to, cs held high. it is specified in nv-s and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac a t midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is expressed in nv-s. analog crosstalk this is the glitch impulse transferred to the output of one dac d ue to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping ldac high. then pulse ldac low and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv-s. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac d ue to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with the ldac pin set low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the m ultiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) this is the difference between an ideal sine wave and its a ttenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in db.
ad5346/ad5347/ad5348 rev. 0 | page 12 of 24 typical performance characteristics code 250 100 0 50 150 200 inl error (lsb) 1.0 0.5 ? 1.0 0 ? 0.5 03331-0-014 t a = 25 c v dd = 5v figure 14. ad5346 typical inl plot code inl error (lsb) 3 0 200 1000 400 600 800 0 ? 1 ? 2 ? 3 2 1 t a = 25 c v dd = 5v 03331-0-015 figure 15. ad5347 typical inl plot code inl error (lsb) 12 0 ? 4 ? 8 8 4 0 4000 1000 2000 3000 ? 12 t a = 25 c v dd = 5v 03331-0-016 figure 16. ad5348 typical inl plot code dnl error (lsb) 250 100 150 0 50 200 ? 0.1 ? 0.2 ? 0.3 0.3 0.1 0.2 0 03331-0-017 t a = 25 c v dd = 5v figure 17. ad5346 typical dnl plot code dnl error (lsb) 0.4 ? 0.4 600 400 800 1000 0 ? 0.6 0.6 0.2 ? 0.2 200 0 t a = 25 c v dd = 5v 03331-0-018 figure 18. ad5347 typical dnl plot code 2000 3000 4000 dnl error (lsb) 0.5 0 ?1.0 1.0 ?0.5 1000 0 03331-0-019 t a = 25 c v dd = 5v figure 19. ad5348 typical dnl plot
ad5346/ad5347/ad5348 rev. 0 | page 13 of 24 v ref (v) error (lsb) 0.5 0.3 0.2 0.1 0.4 ?0.5 ?0.4 0 ?0.3 ?0.2 ?0.1 01234 5 max inl max dnl min inl min dnl 03331-0-031 v dd = 5v t a = 25 c figure 20. ad5346 inl and dnl error vs. v ref temperature ( c) error (lsb) 0.5 0.2 ? 0.5 ? 40 0 ?2 04 0 20 0 ? 0.2 60 80 100 ? 0.4 ? 0.3 ? 0.1 0.1 0.3 0.4 max inl max dnl min inl 03331-0-032 v dd = 5v v ref = 2v min dnl figure 21. ad5346 inl and dnl error vs. temperature temperature ( c) ?1.0 03331-0-033 error (% fsr) 1.0 0.5 ?40 ?20 0 40 20 0 ?0.5 80 60 100 offset error gain error v dd = 5v v ref = 2v figure 22. ad5346 offset error and gain error vs. temperature v dd (v) error (% fsr) 0.2 0 ? 0.6 0 2 1 3 ? 0.4 ? 0.2 456 ? 0.5 ? 0.3 ? 0.1 0.1 03331-0-034 t a = 25 c v ref = 2v offset error gain error figure 23. offset error and gain error vs. v dd sink/source current (ma) v out (v) 5 0 0 2 1 3 3 456 1 2 4 03331-0-035 5v source 3v source 5v sink 3v sink figure 24. v out source and sink current capability dac code i dd (ma) 1.0 0.8 0 zero scale half scale 0.2 0.4 full scale 0.1 0.3 0.5 0.6 0.7 0.9 03331-0-036 v dd = 5v t a = 25 c figure 25. supply current vs. dac code
ad5346/ad5347/ad5348 rev. 0 | page 14 of 24 supply voltage (v) i dd (ma) 1.4 1.2 0 2.5 3.5 3.0 4.0 0.4 0.8 4.5 5.0 5.5 0.2 0.6 1.0 03331-0-037 t a = +105 c t a = +25 c t a = ?40 c v ref = 2v gain = 1 unbuffered figure 26. supply current vs. supply voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 i dd power-down ( a) t a = 25c 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) 03331-0-038 figure 27. power-down current vs. supply voltage vlogic (v) i dd (ma) 2.5 0 0 3 2 1 4 1.5 5 0.5 1.0 2.0 03331-0-039 t a = 25 c v dd = 5v v dd = 3v figure 28. supply current vs. logic input voltage ch2 ch1 v out a t a = 25c v dd = 5v v ref = 5v 03331-0-040 ch1 1v, ch2 5v, time base = 1 s/div ldac figure 29. half-scale settling (? to ? scale code) ch2 ch1 ch1 2v, ch2 200mv, time base = 200 s/div v out a v dd 03331-0-041 t a = 25c v dd = 5v v ref = 2v figure 30. power-on reset to 0 v ch1 ch2 ch1 2.00v, ch2 1.00v, time base = 20 s/div v out 1 03331-0-042 pd figure 31. exiting power-down to midscale
ad5346/ad5347/ad5348 rev. 0 | page 15 of 24 0 3 6 9 12 15 18 21 frequency i dd (ma) 0.8 0.6 1.0 1.2 1.4 03331-0-043 v dd = 3v v dd = 5v figure 32. i dd histogram with v dd = 3 v and v dd = 5 v v out (v) 2.47 2.49 2.48 2.50 1 s/div 03331-0-044 figure 33. ad5348 major code transition glitch energy frequency (hz) db 10 ? 10 ? 60 10 1k 100 10k ? 40 ? 30 100k 1m 10m ? 50 ? 20 0 03331-0-045 figure 34. multiplying bandwidth (s mall signal frequency response) v ref (v) full-scale error (v) 0.02 0.01 ? 0.02 0 2 1 3 ? 0.01 0 456 03331-0-046 v dd = 5v t a = 25 c figure 35. full-scale error vs. v ref 0 1.996 1.997 1.998 1.999 511 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 100 75 50 25 03331-0-047 figure 36. dac-to-dac crosstalk
ad5346/ad5347/ad5348 rev. 0 | page 16 of 24 functional description the ad5346/ad5347/ad5348 are octal resistor-string dacs fabricated by a cmos process with resolutions of 8, 10, and 12 bits, respectively. they are written to using a parallel interface. they operate from single supplies of 2.5 v to 5.5 v, and the output buffer amplifiers offer rail-to-rail output swing. the gain of the buffer amplifiers can be set to 1 or 2 to give an output voltage range of 0 v to v ref or 0 v to 2 v ref. the ad5346/ ad5347/ad5348 have reference inputs that may be buffered to draw virtually no current from the reference source. the devices have a power-down feature that reduces current consumption to only 100 na @ 3 v. digital-to-analog section the architecture of one dac channel consists of a reference buffer and a resistor-string dac followed by an output buffer amplifier. the voltage at the v ref pin provides the reference voltage for the dac. figure 37 shows a block diagram of the dac architecture. because the input coding to the dac is straight binary, the ideal output voltage is given by gain d vv n ref out = 2 where: d is the decimal equivalent of the binary code, which is loaded to the dac register: 0C255 for ad5346 (8 bits) 0C1023 for ad5347 (10 bits) 0C4095 for ad5348 (12 bits) n is the dac resolution. gain is the output amplifier gain (1 or 2). v out a (gain = +1 or +2) v ref ab buf dac register input register resistor string output buffer amplifier reference buffer 03331-0-020 figure 37. single dac channel architecture resistor string the resistor string section is shown in figure 38. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. to output amplifier r r r r r v ref 03331-0-021 figure 38. resistor string dac reference input the dacs operate with an external reference. the ad5346/ ad5347/ad5348 have a reference input for each pair of dacs. the reference inputs may be configured as buffered or unbuffered. this option is controlled by the buf pin. in buffered mode (buf = 1), the current drawn from an external reference voltage is virtually zero because the imped- ance is at least 10 m?. the reference input range is 1 v to v dd . in unbuffered mode (buf = 0), the user can have a reference voltage as low as 0.25 v and as high as v dd because there is no restriction due to headroom and footroom of the reference amplifier. the impedance is still large at typically 90 k? for 0 v to v ref mode and 45 k? for 0 v to 2 v ref mode. if using an external buffered reference (such as ref192), there is no need to use the on-chip buffer. output amplifier the output buffer amplifier is capable of generating output voltages to within 1 mv of either rail. its actual range depends on v ref , gain, the load on v out , and offset error. if a gain of +1 is selected (gain = 0), the output range is 0.001 v to v ref . if a gain of +2 is selected (gain = +1), the output range is 0.001 v to 2 v ref . however, because of clamping, the maximum output is limited to v dd C 0.001 v. the output amplifier is capable of driving a load of 2 k? to gnd or v dd , in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output amplifier can be seen in figure 24. the slew rate is 0.7 v/s with a half-scale settling time to 0.5 lsb (at 8 bits) of 6 s with the output unloaded. see figure 29.
ad5346/ad5347/ad5348 rev. 0 | page 17 of 24 parallel interface the ad5346/ad5347/ad5348 load their data as a single 8-, 10-, or 12-bit word. double-buffered interface the ad5346/ad5347/ad5348 dacs all have double-buffered interfaces consisting of an input register and a dac register. dac data, buf, and gain inputs are written to the input regis- ter under control of the chip select ( cs ) and write ( wr ) pins. access to the dac register is controlled by the ldac function. when ldac is high, the dac register is latched and the input register may change state without affecting the contents of the dac register. however, when ldac is brought low, the dac register becomes transparent and the contents of the input register are transferred to it. the gain and buffer control signals are also double-buffered and are updated only when ldac is taken low. this is useful if the user requires simultaneous updating of all dacs and peripherals. the user can write to all input registers individually and then, by pulsing the ldac input low, all outputs update simultaneously. these parts contain an extra feature whereby the dac register is not updated unless its input register has been updated since the last time that ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the input registers. in the case of the ad5346/ ad5347/ad5348, the part updates the dac register only if the input register has been changed since the last time the dac register was updated. this removes unnecessary crosstalk. clear input ( clr ) clr is an active low, asynchronous clear that resets the input and dac registers. chip select input ( cs ) cs is an active low input that selects the device. write input ( wr ) wr is an active low input that controls writing of data to the device. data is latched into the input register on the rising edge of wr . read input ( rd ) rd is an active low input that controls when data is read back from the internal dac registers. on the falling edge of rd , data is shifted onto the data bus. under the conditions of a high capacitive load and high supplies, the user must ensure that the dynamic current remains at an acceptable level, therefore ensuring that the die temperature is within specification. the die temperature can be calculated as t die = t ambient + v dd ( i dd + i dnamic ) a where i dnamic = cvf and c = capacitance or the data bus v = v dd f = readback frequency load dac input ( ldac ) ldac transfers data from the input register to the dac register, and therefore updates the outputs. the ldac function enables double-buffering of the dac data, gain data, and buf. there are two ldac modes: ? synchronous mode. in this mode, the dac register is updated after new data is read in on the rising edge of the wr input. ldac can be tied permanently low or pulsed as shown in figure 3. ? asynchronous mode. in this mode, the outputs are not updated at the same time that the input register is written to. when ldac goes low, the dac register is updated with the contents of the input register. power-on reset the ad5346/ad5347/ad5348 have a power-on reset function, so that they power up in a defined state. the power-on state is ? normal operation ? reference input buffered ? 0 v to v ref output range ? output voltage set to 0 v both input and dac registers are filled with zeros and remain so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up. power-down mode the ad5346/ad5347/ad5348 have low power consumption, dissipating typically 2.4 mw with a 3 v supply and 5 mw with a 5 v supply. power consumption can be further reduced when the dacs are not in use by putting them into power-down mode, which is selected by taking the pd pin low. when the pd pin is high, the dacs work normally with a typi- cal power consumption of 1 ma at 5 v (0.8 ma at 3 v). in power-down mode, however, the supply current falls to 400 na at 5 v (120 na at 3 v) when the dacs are powered down. not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. this has the advantage that the outputs are three- state while the part is in power-down mode, and provides a defined input condition for whatever is connected to the outputs of the dac amplifiers. the output stage is illustrated in figure 39. resistor string dac power-down circuitry amplifier v ou t 03331-0-022 figure 39. output stage during power-down
ad5346/ad5347/ad5348 rev. 0 | page 18 of 24 the bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are all shut down when the power-down mode is activated. however, the contents of the registers are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s when v dd = 3 v. this is the time from a rising edge on the pd pin to when the output voltage deviates from its power-down voltage. see figure 31. suggested data bus formats in many applications, the gain and buf pins are hardwired. however, if more flexibility is required, they can be included in a data bus. this enables the user to software program gain, giving the option of doubling the resolution in the lower half of the dac range. in a bused system, gain and buf may be treated as data inputs because they are written to the device during a write operation and take effect when ldac is taken low. this means that the reference buffers and the output amplifier gain of multiple dac devices can be controlled using common gain and buf lines. note that gain and buf are not read back during an rd operation. the ad5347 and ad5348 data bus must be at least 10 and 12 bits wide, respectively, and are best suited to a 16-bit data bus system. examples of data formats for putting gain and buf on a 16-bit data bus are shown in figure 40. note that any unused bits above the actual dac data may be used for gain and buf. 03331-0-048 db0db1db2db3db4db5db6db7db8db9 gain xx buf x x = unused bit x db0db1db2db3db4db5db6db7db8db9 gain xx buf db11 db10 ad5347 ad5348 figure 40. ad5347/ad5348 data format for word load with gain and buf data on 16-bit bus table 8. ad5346/ad5347/ad5348 truth table clr ldac cs wr rd a2 a1 a0 function 1 1 1 x x x x x no data transfer 1 1 x 1 1 x x x no data transfer 0 x x x x x x x clear all registers 1 1 0 01 1 0 0 0 load dac a input register 1 1 0 01 1 0 0 1 load dac b input register 1 1 0 01 1 0 1 0 load dac c input register 1 1 0 01 1 0 1 1 load dac d input register 1 1 0 01 1 1 0 0 load dac e input register 1 1 0 01 1 1 0 1 load dac f input register 1 1 0 01 1 1 1 0 load dac g input register 1 1 0 01 1 1 1 1 load dac h input register 1 x 0 1 10 0 0 0 read back dac register a 1 x 0 1 10 0 0 1 read back dac register b 1 x 0 1 10 0 1 0 read back dac register c 1 x 0 1 10 0 1 1 read back dac register d 1 x 0 1 10 1 0 0 read back dac register e 1 x 0 1 10 1 0 1 read back dac register f 1 x 0 1 1 0 1 1 0 read back dac register g 1 x 0 1 10 1 1 1 read back dac register h 1 0 x x 1 x x x update dac registers x x 0 0 0 x x x invalid operation x = dont care
ad5346/ad5347/ad5348 rev. 0 | page 19 of 24 applications information typical application circuits the ad5346/ad5347/ad5348 can be used with a wide range of reference voltages, especially if the reference inputs are configured as unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 v to v dd . more typically, these devices may be used with a fixed, precision reference voltage. figure 41 shows a typical setup for the devices when using an external reference connected to the reference inputs. suitable references for 5 v operation are the ad780, adr381, and ref192 (2.5 v refer- ences). for 2.5 v operation, suitable external references are the ad589 and the ad1580 (1.2 v band gap references). ad5346/ad5347/ ad5348 v out * 0.1 f v dd = 2.5v to 5.5v v dd gnd ad780/adr381/ref192 with v dd = 5v or ad589/ad1580 with v dd = 2.5v v ref * gnd *only one channel of v ref and v out shown 10 f v out v in ext ref 03331-0-024 figure 41. ad5346/ad5347/ad5348 using an external reference driving v dd from the reference voltage if an output range of 0 v to v dd is required, the simplest solution is to connect the reference inputs to v dd . because this supply may not be very accurate and may be noisy, the devices can be powered from the reference voltage, for example, by using a 5 v reference such as the adm663 or adm666, as shown in figure 42. ad5346/ad5347/ ad5348 v out * 0.1 f 6v to 16v v dd gnd v ref * gnd *only one channel of v ref and v out shown 10 f v out(2) v in ext ref 0.1 f gnd sense shdn vset adm663/adm666 03331-0-025 figure 42. using an adm663/adm666 as power and reference to the ad5346/ad5347/ad5348 bipolar operation using the ad5346/ad5347/ad5348 the ad5346/ad5347/ad5348 have been designed for single- supply operation, but a bipolar output range is also possible by using the circuit shown in figure 43. this circuit has an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820, an ad8519, or an op196 as the output amplifier. 5v ext ref gnd v out r2 20k ? r1 10k ? r4 20k ? r3 10k ? 5v +5v ?5v *only one channel of v ref and v out shown 0.1 f 0.1 f 10 f ad820/ad8519/ op196 v in gnd ad5346/ad5347/ ad5348 v out * v dd v ref * 03331-0-026 figure 43. bipolar operation with the ad5346/ ad5347/ad5348 the output voltage for any input code can be calculated as follows: v out = [(1 + r4 / r3 ) ( r2 /( r1 + r2 ) (2 v ref d/2 n )] C r4 v ref / r3 where: d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. v ref is the reference voltage input. with: v ref = 5 v r1 = r3 = 10 k ? r2 = r4 = 20 k ? v dd = 5 v gain = 2 v out = (10 d /2 n ) C 5
ad5346/ad5347/ad5348 rev. 0 | page 20 of 24 decoding multiple ad5346/ad5347/ad5348s the cs pin on these devices can be used in applications to decode a number of dacs. in this application, all dacs in the system receive the same data and wr pulses, but only the cs to one of the dacs will be active at any one time, so data will only be written to the dac whose cs is low. the 74hc139 is used as a 2-line to 4-line decoder to address any of the dacs in the system. to prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. figure 44 shows a diagram of a typical setup for decoding multiple devices in a system. once data has been written sequentially to all dacs in a system, all the dacs can be updated simultaneously using a common ldac line. a com- mon clr line can also be used to reset all dac outputs to 0 v. enable coded a ddress 1g 1a 1b v dd v cc 74hc139 dgnd 1y0 1y1 1y2 1y3 a0 a1 a2 wr ldac clr data inputs data inputs data inputs data inputs data bus a0 a1 a2 wr ldac clr cs a0 a1 a2 wr ldac clr cs ad5346/ad5347 /ad5348 a0 a1 a2 wr ldac clr cs a0 a1 a2 wr ldac clr cs ad5346/ad5347 /ad5348 ad5346/ad5347 /ad5348 ad5346/ad5347 /ad5348 03331-0-027 figure 44. decoding multiple dac devices ad5346/ad5347/ad5348 as digitally programmable window detectors a digitally programmable upper/lower limit detector using two of the dacs in the ad5346/ad5347/ad5348 is shown in figure 45. any pair of dacs in the device may be used, but for simplicity the description refers to dacs a and b. the upper and lower limits for the test are loaded to dacs a and b which, in turn, set the limits on the cmp04. if a signal at the v in input is not within the programmed window, an led indicates the fail condition. 5v gnd v ref ab v dd v in fail pass 1k ? 1k ? pass/ fail 1/6 74hc05 1/2 cmp04 v ref 0.1 f 10 f v out b v out a ad5346/ad5347/ ad5348 03331-0-028 figure 45. programmable window detector programmable current source figure 46 shows the ad5346/ad5347/ad5348 used as the control element of a programmable current source. in this example, the full-scale current is set to 1 ma. the output voltage from the dac is applied across the current setting resistor of 4.7 k? in series with the 470 ? adjustment potentiometer, which gives an adjustment of about 5%. suitable transistors to place in the feedback loop of the ampli- fier include the bc107 and the 2n3904, which enable the current source to operate from a minimum v source of 6 v. the operating range is determined by the operating characteristics of the transistor. suitable amplifiers include the ad820 and the op295, both having rail-to-rail operation on their outputs. the current for any digital input code and resistor value can be calculated as follows: ma r d vgi n ref )2( = where: g is the gain of the buffer amplifier (1 or 2). d is the digital input code. n is the dac resolution (8, 10, or 12 bits). r is the sum of the resistor plus adjustment potentiometer in k?. v dd = 5v 5v load v source ext ref gnd v out 4.7k ? 470 ? *only one channel of v ref and v out shown 0.1 f 0.1 f 10 f v in gnd ad5346/ad5347/ ad5348 v dd v ref *v out * 03331-0-029 figure 46. programmable current source
ad5346/ad5347/ad5348 rev. 0 | page 21 of 24 coarse and fine adjustment using the ad5346/ad5347/ad5348 two of the dacs in the ad5346/ad5347/ad5348 can be paired together to form a coarse and fine adjustment function, as shown in figure 47. as with the window comparator previously described, the description refers to dacs a and b. dac a provides the coarse adjustment, while dac b provides the fine adjustment. varying the ratio of r1 and r2 changes the relative effect of the coarse and fine adjustments. with the resistor values shown, the output amplifier has unity gain for the dac a output, so the output range is 0 v to (v ref C 1 lsb). for dac b, the amplifier has a gain of 7.6 10 C3 , giving dac b a range equal to 2 lsbs of dac a. the circuit is shown with a 2.5 v reference, but reference voltages up to v dd may be used. the op amps indicated allow a rail-to-rail output swing. ad780/adr381/ref192 with v dd = 5v v dd = 5v v out 5v ext ref v out v in gnd gnd ad5346/ad5347/ ad5348 v out b v out a v dd v ref ab r1 390 ? r4 390 ? r2 51.2k ? r3 51.2k ? 0.1 f 0.1 f 10 f 03331-0-030 figure 47. coarse and fine adjustment power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5346/ad5347/ ad5348 is mounted should be designed so that the analog and digital sections are separated and are confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes because it gives the best shielding. digital and analog ground planes should be joined in one place only. if the ad5346/ad5347/ad5348 is the only device requiring an agnd-to-dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the ad5346/ ad5347/ad5348. if the ad5346/ad5347/ad5348 is in a system where multiple devices require agnd-to-dgnd connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the ad5346/ad5347/ad5348. the ad5346/ad5347/ad5348 should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the device should use the largest trace possible to provide low impedance paths and to reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side.
ad5346/ad5347/ad5348 rev. 0 | page 22 of 24 table 9. overview of ad53xx parallel devices additional pin functio ns part no. resolution dnl v ref pins settling time buf gain hben clr package pins singles AD5330 8 0.25 1 6 s 9 9 9 tssop 20 ad5331 10 0.5 1 7 s 9 9 tssop 20 ad5340 12 1.0 1 8 s 9 9 9 tssop 24 ad5341 12 1.0 1 8 s 9 9 9 9 tssop 20 duals ad5332 8 0.25 2 6 s 9 tssop 20 ad5333 10 0.5 2 7 s 9 9 9 tssop 24 ad5342 12 1.0 2 8 s 9 9 9 tssop 28 ad5343 12 1.0 1 8 s 9 9 tssop 20 quads ad5334 8 0.25 2 6 s 9 9 tssop 24 ad5335 10 0.5 2 7 s 9 9 tssop 24 ad5336 10 0.5 4 7 s 9 9 tssop 28 ad5344 12 1.0 4 8 s tssop 28 octals ad5346 8 0.25 4 6 s 9 9 9 tssop, lfcsp 38, 40 ad5347 10 0.5 4 7 s 9 9 9 tssop, lfcsp 38, 40 ad4348 12 1.0 4 8 s 9 9 9 tssop, lfcsp 38, 40 table 10. overview of ad53xx serial devices part no. resolution dnl v ref pins settling time interface package pins singles ad5300 8 0.25 0 (v ref = v dd ) 4 s spi? sot-23, msop 6, 8 ad5310 10 0.5 0 (v ref = v dd ) 6 s spi sot-23, msop 6, 8 ad5320 12 1.0 0 (v ref = v dd ) 8 s spi sot-23, msop 6, 8 ad5301 8 0.25 0 (v ref = v dd ) 6 s 2-wire sot-23, msop 6, 8 ad5311 10 0.5 0 (v ref = v dd ) 7 s 2-wire sot-23, msop 6, 8 ad5321 12 1.0 0 (v ref = v dd ) 8 s 2-wire sot-23, msop 6, 8 duals ad5302 8 0.25 2 6 s spi msop 8 ad5312 10 0.5 2 7 s spi msop 8 ad5322 12 1.0 2 8 s spi msop 8 ad5303 8 0.25 2 6 s spi tssop 16 ad5313 10 0.5 2 7 s spi tssop 16 ad5323 12 1.0 2 8 s spi tssop 16 quads ad5304 8 0.25 1 6 s spi msop 10 ad5314 10 0.5 1 7 s spi msop 10 ad5324 12 1.0 1 8 s spi msop 10 ad5305 8 0.25 1 6 s 2-wire msop 10 ad5315 10 0.5 1 7 s 2-wire msop 10 ad5325 12 1.0 1 8 s 2-wire msop 10 ad5306 8 0.25 4 6 s 2-wire tssop 16 ad5316 10 0.5 4 7 s 2-wire tssop 16 ad5326 12 1.0 4 8 s 2-wire tssop 16 ad5307 8 0.25 2 6 s spi tssop 16 ad5317 10 0.5 2 7 s spi tssop 16 ad5327 12 1.0 2 8 s spi tssop 16 octals ad5308 8 0.25 2 6 s spi tssop 16 ad5318 10 0.5 2 7 s spi tssop 16 ad5328 12 1.0 2 8 s spi tssop 16
ad5346/ad5347/ad5348 rev. 0 | page 23 of 24 outline dimensions 38 20 19 1 9.80 9.70 9.60 pin 1 seating plane 0.15 0.05 0.50 bsc 1.20 max 0.27 0.17 0.20 0.09 8 0 4.50 4.40 4.30 6.40 bsc 0.70 0.60 0.45 compliant to jedec standards mo-153bd-1 coplanarity 0.10 figure 48. 38-lead thin shrink small outline package [tssop] (ru-38) dimensions shown in millimeters 1 40 10 11 31 30 21 20 bottom view 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicato r 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min compliant to jedec standards mo-220-vjjd-2 figure 49. 40-lead lead frame chip scale package [lfcsp] (cp-40) dimensions shown in millimeters
ad5346/ad5347/ad5348 rev. 0 | page 24 of 24 ordering guides table 11. ad5346 ordering guide model temperature range package description package option ad5346bru C40c to +105c tssop (thin sh rink small outline package) ru-38 ad5346bru-reel C40c to +105c tssop (thin shrink small outline package) ru-38 ad5346bru-reel7 C40c to +105c tssop (thi n shrink small outline package) ru-38 ad5346bcp C40c to +105c lfcsp (lead frame chip scale package) cp-40 ad5346bcp-reel C40c to +105c lfcsp (lea d frame chip scale package) cp-40 ad5346bcp-reel7 C40c to +105c lfcsp (l ead frame chip scale package) cp-40 table 12. ad5347 ordering guide model temperature range package description package option ad5347bru C40c to +105c tssop (thin sh rink small outline package) ru-38 ad5347bru-reel C40c to +105c tssop (thin shrink small outline package) ru-38 ad5347bru-reel7 C40c to +105c tssop (thi n shrink small outline package) ru-38 ad5347bcp C40c to +105c lfcsp (lead frame chip scale package) cp-40 ad5347bcp-reel C40c to +105c lfcsp (lea d frame chip scale package) cp-40 ad5347bcp-reel7 C40c to +105c lfcsp (l ead frame chip scale package) cp-40 table 13. ad5348 ordering guide model temperature range package description package option ad5348bru C40c to +105c tssop (thin sh rink small outline package) ru-38 ad5348bru-reel C40c to +105c tssop (thin shrink small outline package) ru-38 ad5348bru-reel7 C40c to +105c tssop (thi n shrink small outline package) ru-38 ad5348bcp C40c to +105c lfcsp (lead frame chip scale package) cp-40 ad5348bcp-reel C40c to +105c lfcsp (lea d frame chip scale package) cp-40 ad5348bcp-reel7 C40c to +105c lfcsp (l ead frame chip scale package) cp-40 ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c03331C0 C11/03(0)

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